Muse Semiconductor and True Circuits Partner to Lower Academic Chip Design Barriers

By integrating True Circuits’ commercial IP into Muse’s multi-project wafer (MPW) services, the program eliminates the common hurdle of sourcing reliable timing components on limited academic budgets. Participants gain access to general-purpose PLLs across TSMC process nodes including 180nm, 65nm, 28nm, and 16nm. This allows engineering teams to mirror commercial development workflows while maintaining the necessary intellectual property protections and foundry compliance protocols.

To facilitate this, Muse is establishing a self-service portal featuring technical guidelines, application notes, and training resources. Support will be tiered, with Muse providing initial guidance and True Circuits handling advanced technical inquiries. According to Bill Isaacson, General Manager of Muse Semiconductor, the partnership serves to bridge the gap between classroom theory and professional design environments. Brian Gardner, V.P. of Business Development at True Circuits, noted that the effort aligns with the company’s broader commitment to open-source development tools, ensuring that the next generation of engineers can test designs with industry-standard performance metrics.