Synopsys and Intel Foundry certify AI-driven EDA flows for 14A process

The partnership integrates multiphysics analysis directly into the design cycle, allowing engineers to address power integrity, thermal constraints, and electromagnetic effects during the initial development phases. This shift moves beyond traditional scaling, enabling what the companies describe as system-aware co-design. By embedding these capabilities, designers can optimize power, performance, and area (PPA) across the silicon, package, and IP domains before reaching the tapeout stage.

Multi-die architectures, now central to modern AI hardware, receive specific support through the Synopsys 3DIC Compiler platform. This toolset now manages Intel’s EMIB and EMIB-T packaging technologies, facilitating automated routing for UCIe and HBM. Concurrent analysis of these interconnects alongside thermal gradients helps catch architectural bottlenecks early. To further accelerate readiness, Synopsys is providing a broad IP portfolio for the 14A node, including PCIe 7.0, 224G SerDes, and USB 4, which are designed to reduce integration risk for complex system-on-chip configurations.